1. Field of the Invention
The invention relates to a hetero-junction field effect transistor.
2. Description of the Related Art
FIG. 1 illustrates an example of a conventional hetero-junction field effect transistor (HJFET). The illustrated hetero-junction field effect transistor 100 is comprised of a semi-insulating InP substrate 110, an undoped InP buffer layer 120 junctioned on the semi-insulating InP substrate 110, an n-type InP channel layer 130 junctioned on the undoped InP buffer layer 120, an undoped InAlAs gate insulating layer 140 junctioned on the n-type InP channel layer 130, and an n-type InGaAs cap layer 150 junctioned on the undoped InAlAs gate insulating layer 140.
A source electrode 160 and a drain electrode 170 are formed on the n-type InGaAs cap layer 150 in ohmic contact.
The n-type InGaAs cap layer 150 is formed with an opening, and a gate electrode 180 is formed on the undoped InAlAs gate insulating layer 140 in the opening of the n-type InGaAs cap layer 150 in Schottky contact.
In an operation, if a current is made to run through the gate electrode 180, a current runs from the source electrode 160 to the drain electrode 170.
There have been suggested various hetero junction field effect transistors so far.
For instance, Japanese Unexamined Patent Publication No. 4-241428 has suggested a field effect transistor comprising an InP semiconductor substrate, a first undoped semiconductor layer formed on the InP semiconductor substrate, an n-type heavily doped InP channel layer formed on the first undoped semiconductor layer and having crystal structure which almost matches in lattice to the first undoped semiconductor layer, a second undoped InP semiconductor layer formed on the InP channel layer and having superior electron-transfer characteristic, a third undoped Al.sub.X In.sub.1-X As (0.4.ltoreq.X.ltoreq.0.6) semiconductor layer formed on the second undoped InP semiconductor layer, source and drain electrode formed on the third semiconductor layer, and a gate electrode formed on the second undoped InP semiconductor layer in an opening formed throughout the third semiconductor layer.
Japanese Unexamined Patent Publication No. 5-102197 has suggested a field effect transistor comprising a semi-insulating InP semiconductor substrate, a buffer layer formed on the substrate, an InP channel layer formed on the buffer layer, an In.sub.Y Ga.sub.1-Y As (0.45.ltoreq.Y.ltoreq.0.65) spacer layer formed on the InP channel layer, an electron-donating layer formed on the spacer layer and composed of Al.sub.X In.sub.1-X As (0.4.ltoreq.X.ltoreq.0.6), a contact layer formed on the electron-donating layer, source and drain electrodes formed on the contact layer, and a gate electrode formed on the electron-donating layer in an opening formed throughout the contact layer. The spacer layer is designed to have such a thickness that secondary electron gas is formed in the channel layer due to electrons supplied from the electron-donating layer 5.
Japanese Unexamined Patent Publication No. 6-84960 has suggested a hetero-junction field effect transistor comprising a semi-insulating InP substrate, a first i-In.sub.0.52 Al.sub.0.48 As layer, an i-InP layer, an i-In.sub.X Ga.sub.1-X AS layer, an i-InP layer, a second i-In.sub.0.52 Al.sub.0.48 As layer, an n-In.sub.0.52 Al.sub.0.48 As layer, a third i-In.sub.0.52 Al.sub.0.48 As layer, and an n-In.sub.0.53 Al.sub.0.47 As layer, source and drain electrodes formed on the n-In.sub.0.53 Al.sub.0.47 As layer in ohmic contact, and a gate electrode formed on third i-In.sub.0.52 Al.sub.0.48 As layer in an opening formed throughout the n-In.sub.0.53 Al.sub.0.47 As layer. The layers are formed on the semi-insulating InP substrate in this order.
The above-mentioned conventional hetero-junction field effect transistors are accompanied with the following problem.
For instance, in the conventional hetero-junction field effect transistor illustrated in FIG. 1, the cap layer 150 is composed of InGaAs. Hence, as illustrated in FIG. 2, a conduction band offset at an interface between the cap layer 150 and the gate insulating layer 140, which is equal to about 0.51 eV, is greater than a conduction band offset between the channel layer 130 and the gate insulating layer 140, which is equal to about 0.28 eV. This results in that an electron barrier is raised, and if the cap layer 150 is designed to make ohmic contact with the channel layer 130 through a non-alloy layer, a contact resistance therebetween would be increased.
Hence, source and drain resistances are also increased, resulting in reduction in power gain, increase in noise figure, and reduction in power addition efficiency to be obtained when a hetero-junction field effect transistor is operated with high-level signals.